This invention relates to polishing pads for polishing semiconductor wafers, and more particularly to determining performance characteristics of a production lot of polishing pads using discriminant analysis.
Semiconductor wafers are generally prepared from a single crystal ingot sliced into individual wafers. The wafers are subjected to several processing operations to reduce the thickness of the wafer, remove damage caused by the slicing operation, and create a highly reflective surface. In conventional wafer shaping processes, a lapping operation is performed on the front and back surfaces of the wafer using an abrasive slurry and a set of rotating lapping plates. The lapping operation reduces the thickness of the wafer to remove surface damage induced by the slicing operation and to make the opposing side surfaces of each wafer flat and parallel. Upon completion of the lapping operation, the wafers are subjected to a chemical etching operation to reduce further the thickness of the wafer and remove mechanical damage produced by the prior processing operations. One side surface of each wafer (often called the "front" side of the wafer) is then polished using a polishing pad, a colloidal silica slurry (polishing slurry) and a chemical etchant to ensure that the wafer has a highly reflective, damage-free surface. This invention relates in particular to the polishing process.
Semiconductor wafers used as starting materials for the fabrication of integrated circuits must meet certain surface flatness requirements. Such wafers must be particularly flat to print circuits on them by, for example, an electron beam-lithographic or photolithographic process. Wafer flatness in the focal point of the electron beam delineator or optical printer is important for uniform imaging in the electron beam-lithographic and photolithographic processes. The flatness of the wafer surface directly influences device line width capability, process latitude, yield and throughput. The continuing reduction in device geometry and increasingly stringent device fabrication specifications force manufacturers of semiconductor wafers to prepare increasingly flatter wafers. Wafers can be characterized for flatness in terms of a global flatness variation parameter (for example, total thickness variation ("TTV")) or in terms of a local site flatness variation parameter (e.g., Site Total Indicated Reading ("STIR") or Site Focal Plane Deviation ("SFPD")) as measured against a reference plane of the wafer (e.g., Back Reference Center Focus ("SBIR") or Site Best Fit Reference Plane ("SFQR")). A more detailed discussion of the characterization of wafer flatness can be found in F. S HIMURA, Semiconductor Silicon Crystal Technology 191-195 (Academic Press 1989).
Because a wafer's flatness is of paramount importance, production variables affecting wafer flatness are closely monitored. The quality of the polishing pad used to polish the wafer, for example, directly affects the flatness characteristics of the polished wafer. Therefore, an accurate assessment of the polishing pad quality, and particularly identification of bad lots, is important to semiconductor wafer production. Historically, polishing pad performance between production lots has been variable, due to minor variations in the supplier's manufacturing process. In contrast, within a production lot, the quality of the pads is typically consistent because each pad is stamped from the same raw material. Therefore, each production lot of polishing pads must be separately assessed to determine its quality and usefulness. To assess the quality of a particular production lot of wafers, several pads must be tested on Grade I semiconductor material to assess the overall quality of the pad. Grade I semiconductor material is expensive to manufacture, and its use in testing pad quality places the polished semiconductor material at risk of flatness degradation which may render the wafer unsuitable for use. Therefore, any reduction in the amount of Grade I material placed at risk during the testing process is beneficial.
Assessing the quality of a production lot of wafers traditionally has been a qualitative task, based upon the wafer shape and other flatness measures. According to the prior methodology, once a current production lot of good polishing pads is exhausted, a new production lot of pads is used in the wafer polishing process. When these new pads are installed on the polishers, their quality is unknown. As the new pads are broken in, if the quality of wafer flatness remains high, the pads are considered good and not analyzed further. Alternately, if wafer quality appears to suffer and substandard polishing pads are suspected, pad quality is evaluated. By evaluating the flatness of the wafers with different flatness measures, as described above, the questionable production lot is characterized as bad or marginal. This in-use type evaluation process is time consuming and costly. Because the pads are used in production before their quality is appreciated, they place many Grade I wafers at risk of flatness degradation and possible loss before a problem is identified. This problem is exacerbated if quality problems associated with the pads are difficult to detect and go undetected for significant periods. Once the lot quality is determined to be bad, the lot is rejected and returned to the pad manufacturer. Marginal production lots are subject to further pad testing and further destruction of Grade I material until a determination of lot quality can be made. Because this process is time consuming and subjects many Grade I wafers to risk of flatness degradation and potential loss, a more efficient and less costly methodology for determining pad quality is necessary.